Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided  by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...

متن کامل

Design of High Speed and Low Power 4t Sram Cell

Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also ...

متن کامل

Nanoprobing SRAM Bit Cells with High-Speed Pulses

For a number of years, in-die SRAM transistors have been successfully probed using direct current (dc) nanoprobing to reveal faults for failure analysis and to verify in-die parametric performance for the engineering design loop.[1-5] These slow dc tests are needed for measuring subnanoampere gate and channel leakages. There has recently been interest in exploring the value of high-speed testin...

متن کامل

High Density Four-transistor Sram Cell with Low Power Consumption

This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional sixtransistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform...

متن کامل

New Low-Power and High-Speed 9T SRAM cell in Dynamic Domino Logic

This study presents the design of low power 9T SRAM cell using dynamic domino logic to achieve low power dissipation. The internal structure of the proposed 9T SRAM has cross coupled dynamic inverters which periodically updates the internal node voltage levels which, increase the read and write stability of the circuit. The SRAM design also has charge keeper transistor which resolves the proble...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: International Journal of Computer Applications

سال: 2016

ISSN: 0975-8887

DOI: 10.5120/ijca2016909859